library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity vup_line1 is  --vup_line1
port(
		clk: in std_ulogic;
		flag: in std_ulogic;
		flag2: in std_ulogic;
		flgout2: in std_ulogic;
		frame: in integer range 0 to 4096;
		addr1: in std_ulogic_vector(15 downto 0); 
		addr2: in std_ulogic_vector(15 downto 0); 
		addr3: in std_ulogic_vector(15 downto 0); 
		addr4: in std_ulogic_vector(15 downto 0); 
		addr5: in std_ulogic_vector(15 downto 0); 
		addr6: in std_ulogic_vector(15 downto 0); 
		addr7: in std_ulogic_vector(15 downto 0);
		e1: in std_ulogic_vector(31 downto 0);
		e2: in std_ulogic_vector(31 downto 0);
		e3: in std_ulogic_vector(31 downto 0);
		e4: in std_ulogic_vector(31 downto 0);
		e5: in std_ulogic_vector(31 downto 0);
		e6: in std_ulogic_vector(31 downto 0);
		e7: in std_ulogic_vector(31 downto 0);
		b_len: in integer range 50 to 512;
		llrq: out std_ulogic_vector(31 downto 0)
		--vup_outflag: out std_ulogic
		);
end vup_line1;


architecture bev of vup_line1 is

signal t1,t2:signed(18 downto 0);
signal temp1,temp2:std_ulogic_vector(18 downto 0);
signal t11,t22:std_ulogic_vector(3 downto 0);
signal ee1,ee2,ee3,ee4,ee5,ee6,ee7: std_ulogic_vector(15 downto 0);
signal eee1,eee2,eee3,eee4,eee5,eee6,eee7: std_ulogic_vector(15 downto 0);

begin

--**********the first depth data operation***************
process(clk,flag2,frame,b_len,e1(31 downto 16),e2(31 downto 16),e3(31 downto 16),e4(31 downto 16),e5(31 downto 16),e6(31 downto 16),e7(31 downto 16),addr1(15 downto 8),addr2(15 downto 8),addr3(15 downto 8),addr4(15 downto 8),addr5(15 downto 8),addr6(15 downto 8),addr7(15 downto 8))
variable var:unsigned(12 downto 0);
variable temp:integer range 0 to 4096;
begin
  if flag2='1' then
  if clk'event and clk='1' then
	if frame <= b_len-1 and frame >= 0 then --[0,49]
		var := (others=>'0');
		ee1 <= (others=>'0');
		ee2 <= (others=>'0');
		ee3 <= (others=>'0');
		ee4 <= (others=>'0');
		ee5 <= (others=>'0');
		ee6 <= (others=>'0');
		ee7 <= (others=>'0');
		
	elsif frame <= (2*b_len-1) and frame > b_len-1 then --(49,99]
		temp:=(frame-b_len);
		var := to_unsigned(temp,13);
		if unsigned(addr1(15 downto 8)) < var(7 downto 0) then
		    ee1 <= e1(31 downto 16);
		else
		    ee1 <= (others=>'0');
		end if;
		ee2 <= (others=>'0');
		ee3 <= (others=>'0');
		ee4 <= (others=>'0');
		ee5 <= (others=>'0');
		ee6 <= (others=>'0');
		ee7 <= (others=>'0');
		
		
	elsif frame <= (3*b_len-1) and frame > (2*b_len-1) then --(99,149]
		temp:=(frame-2*b_len);
		var := to_unsigned(temp,13);
		ee1 <= e1(31 downto 16);
		if unsigned(addr2(15 downto 8))  < var(7 downto 0) then
		    ee2 <= e2(31 downto 16);
		else
		    ee2 <= (others=>'0');
		end if;
		ee3 <= (others=>'0');
		ee4 <= (others=>'0');
		ee5 <= (others=>'0');
		ee6 <= (others=>'0');
		ee7 <= (others=>'0');
		

	elsif frame <= (4*b_len-1) and frame > (3*b_len-1)  then --(149,199]
		temp:=(frame-3*b_len);
		var := to_unsigned(temp,13);
		ee1 <= e1(31 downto 16);
		ee2 <= e2(31 downto 16);
		if unsigned(addr3(15 downto 8)) < var(7 downto 0) then
		    ee3 <= e3(31 downto 16);
	 	else
		    ee3 <= (others=>'0');
	 	end if;
		ee4 <= (others=>'0');
		ee5 <= (others=>'0');
		ee6 <= (others=>'0');
		ee7 <= (others=>'0');
	    
	elsif frame <= (5*b_len-1) and frame > (4*b_len-1) then --(199,249]
		temp:=(frame-4*b_len);
		var := to_unsigned(temp,13);
		ee1 <= e1(31 downto 16);
		ee2 <= e2(31 downto 16);
		ee3 <= e3(31 downto 16);
		if unsigned(addr4(15 downto 8)) < var(7 downto 0) then
		    ee4 <= e4(31 downto 16);
    	else
		    ee4 <= (others=>'0');
   	end if;
		ee5 <= (others=>'0');
		ee6 <= (others=>'0');
		ee7 <= (others=>'0');

	elsif frame <= (6*b_len-1) and frame > (5*b_len-1)  then --(249,299]
		temp:=(frame-5*b_len);
		var := to_unsigned(temp,13);
	   ee1 <= e1(31 downto 16);
		ee2 <= e2(31 downto 16);
      ee3 <= e3(31 downto 16);
      ee4 <= e4(31 downto 16);
		if unsigned(addr5(15 downto 8)) < var(7 downto 0) then
		    ee5 <= e5(31 downto 16);
	  	else
		    ee5 <= (others=>'0');
	  	end if;
		ee6 <= (others=>'0');
		ee7 <= (others=>'0');
		
	elsif frame <= (7*b_len-1) and frame > (6*b_len-1) then --(299,349]
		temp:=(frame-6*b_len);
		var := to_unsigned(temp,13);
	   ee1 <= e1(31 downto 16);
		ee2 <= e2(31 downto 16);
      ee3 <= e3(31 downto 16);
		ee4 <= e4(31 downto 16);
    	ee5 <= e5(31 downto 16);
		if unsigned(addr6(15 downto 8)) < var(7 downto 0) then
		    ee6 <= e6(31 downto 16);
	  	else
		    ee6 <= (others=>'0');
	  	end if;
		ee7 <= (others=>'0');
		
	elsif frame <= (8*b_len-1) and frame > (7*b_len-1) then --(349,399]
		temp:=(frame-7*b_len);
		var := to_unsigned(temp,13);
	   ee1 <= e1(31 downto 16);
		ee2 <= e2(31 downto 16);
      ee3 <= e3(31 downto 16);
    	ee4 <= e4(31 downto 16);
    	ee5 <= e5(31 downto 16);
    	ee6 <= e6(31 downto 16);
		if unsigned(addr7(15 downto 8)) < var(7 downto 0) then
		    ee7 <= e7(31 downto 16);
	  	else
		    ee7 <= (others=>'0');
	  	end if;
		
	else
	   ee1 <= e1(31 downto 16);
		ee2 <= e2(31 downto 16);
      ee3 <= e3(31 downto 16);
		ee4 <= e4(31 downto 16);
      ee5 <= e5(31 downto 16);
      ee6 <= e6(31 downto 16);
      ee7 <= e7(31 downto 16);
	end if;
	end if;
	end if;
end process;

process(clk,flag2,ee1,ee2,ee3,ee4,ee5,ee6,ee7)
 begin
   if flag2='1' then
 if clk'event and clk='1' then 
   t1 <=signed(ee1(15)&ee1(15)&ee1(15)&ee1) +
		  signed(ee2(15)&ee2(15)&ee2(15)&ee2) +
		  signed(ee3(15)&ee3(15)&ee3(15)&ee3) +
		  signed(ee4(15)&ee4(15)&ee4(15)&ee4) +
		  signed(ee5(15)&ee5(15)&ee5(15)&ee5) +
		  signed(ee6(15)&ee6(15)&ee6(15)&ee6) +
		  signed(ee7(15)&ee7(15)&ee7(15)&ee7);
 end if;
 end if;
end process;

temp1 <= std_ulogic_vector(t1);
t11 <= flag&flag2&flgout2&temp1(18);

process(clk,temp1,t1)
  begin
    if clk'event and clk='1' then
      if ((t11="1100") and ((temp1(17) or temp1(16) or temp1(15) or temp1(14))='1')) then
        llrq(31 downto 16) <= "0011111111111111";
      elsif ((t11="1100") and ((temp1(17) or temp1(16) or temp1(15) or temp1(14))='0')) then
        llrq(31 downto 16) <= temp1(18)&temp1(14 downto 0);
      elsif ((t11="1101") and ((temp1(17) and temp1(16) and temp1(15) and temp1(14))='0')) then
        llrq(31 downto 16) <= "1100000000000001";
      elsif ((t11="1101") and ((temp1(17) and temp1(16) and temp1(15) and temp1(14))='1')) then
        llrq(31 downto 16) <= temp1(18)&temp1(14 downto 0);
      else
        llrq(31 downto 16) <= (others=>'0');
      end if;	
	end if;
end process;

--**********the second depth data operation***************
process(clk,flag2,frame,b_len,e1(15 downto 0),e2(15 downto 0),e3(15 downto 0),e4(15 downto 0),e5(15 downto 0),e6(15 downto 0),e7(15 downto 0),addr1(7 downto 0),addr2(7 downto 0),addr3(7 downto 0),addr4(7 downto 0),addr5(7 downto 0),addr6(7 downto 0),addr7(7 downto 0))
variable var:unsigned(12 downto 0);
variable temp:integer range 0 to 4096;
begin
  if flag2='1' then
  if clk'event and clk='1' then
	if frame <= b_len-1 and frame >= 0 then --[0,49]
		var := (others=>'0');
		eee1 <= (others=>'0');
		eee2 <= (others=>'0');
		eee3 <= (others=>'0');
		eee4 <= (others=>'0');
		eee5 <= (others=>'0');
		eee6 <= (others=>'0');
		eee7 <= (others=>'0');
		
	elsif frame <= (2*b_len-1) and frame > b_len-1 then --(49,99]
		temp:=(frame-b_len);
		var := to_unsigned(temp,13);
		if unsigned(addr1(7 downto 0)) < var(7 downto 0) then
		    eee1 <= e1(15 downto 0);
		else
		    eee1 <= (others=>'0');
		end if;
		eee2 <= (others=>'0');
		eee3 <= (others=>'0');
		eee4 <= (others=>'0');
		eee5 <= (others=>'0');
		eee6 <= (others=>'0');
		eee7 <= (others=>'0');
			
	elsif frame <= (3*b_len-1) and frame > (2*b_len-1) then --(99,149]
		temp:=(frame-2*b_len);
		var := to_unsigned(temp,13);
		eee1 <= e1(15 downto 0);
		if unsigned(addr2(7 downto 0))  < var(7 downto 0) then
		    eee2 <= e2(15 downto 0);
		else
		    eee2 <= (others=>'0');
		end if;
		eee3 <= (others=>'0');
		eee4 <= (others=>'0');
		eee5 <= (others=>'0');
		eee6 <= (others=>'0');
		eee7 <= (others=>'0');
		

	elsif frame <= (4*b_len-1) and frame > (3*b_len-1)  then --(149,199]
		temp:=(frame-3*b_len);
		var := to_unsigned(temp,13);
		eee1 <= e1(15 downto 0);
		eee2 <= e2(15 downto 0);
		if unsigned(addr3(7 downto 0)) < var(7 downto 0) then
		    eee3 <= e3(15 downto 0);
	 	else
		    eee3 <= (others=>'0');
	 	end if;
		eee4 <= (others=>'0');
		eee5 <= (others=>'0');
		eee6 <= (others=>'0');
		eee7 <= (others=>'0');
	    
	elsif frame <= (5*b_len-1) and frame > (4*b_len-1) then --(199,249]
		temp:=(frame-4*b_len);
		var := to_unsigned(temp,13);
		eee1 <= e1(15 downto 0);
		eee2 <= e2(15 downto 0);
		eee3 <= e3(15 downto 0);
		if unsigned(addr4(7 downto 0)) < var(7 downto 0) then
		    eee4 <= e4(15 downto 0);
    	else
		    eee4 <= (others=>'0');
		end if;
		eee5 <= (others=>'0');
		eee6 <= (others=>'0');
		eee7 <= (others=>'0');

	elsif frame <= (6*b_len-1) and frame > (5*b_len-1)  then --(249,299]
		temp:=(frame-5*b_len);
		var := to_unsigned(temp,13);
	   eee1 <= e1(15 downto 0);
		eee2 <= e2(15 downto 0);
      eee3 <= e3(15 downto 0);
      eee4 <= e4(15 downto 0);
		if unsigned(addr5(7 downto 0)) < var(7 downto 0) then
		    eee5 <= e5(15 downto 0);
	  	else
		    eee5 <= (others=>'0');
	  	end if;
		eee6 <= (others=>'0');
		eee7 <= (others=>'0');
		
	elsif frame <= (7*b_len-1) and frame > (6*b_len-1) then --(299,349]
		temp:=(frame-6*b_len);
		var := to_unsigned(temp,13);
	   eee1 <= e1(15 downto 0);
		eee2 <= e2(15 downto 0);
      eee3 <= e3(15 downto 0);
		eee4 <= e4(15 downto 0);
    	eee5 <= e5(15 downto 0);
		if unsigned(addr6(7 downto 0)) < var(7 downto 0) then
		    eee6 <= e6(15 downto 0);
	  	else
		    eee6 <= (others=>'0');
	  	end if;
		eee7 <= (others=>'0');
		
	elsif frame <= (8*b_len-1) and frame > (7*b_len-1) then --(349,399]
		temp:=(frame-7*b_len);
		var := to_unsigned(temp,13);
	   eee1 <= e1(15 downto 0);
		eee2 <= e2(15 downto 0);
      eee3 <= e3(15 downto 0);
    	eee4 <= e4(15 downto 0);
    	eee5 <= e5(15 downto 0);
    	eee6 <= e6(15 downto 0);
		if unsigned(addr7(7 downto 0)) < var(7 downto 0) then
		    eee7 <= e7(15 downto 0);
	  	else
		    eee7 <= (others=>'0');
	  	end if;
		
	else
	   eee1 <= e1(15 downto 0);
		eee2 <= e2(15 downto 0);
      eee3 <= e3(15 downto 0);
		eee4 <= e4(15 downto 0);
      eee5 <= e5(15 downto 0);
      eee6 <= e6(15 downto 0);
      eee7 <= e7(15 downto 0);
	end if;
	end if;
	end if;
end process;

process(clk,flag2,eee1,eee2,eee3,eee4,eee5,eee6,eee7)
 begin
   if flag2='1' then
 if clk'event and clk='1' then 
   t2 <=signed(eee1(15)&eee1(15)&eee1(15)&eee1) +
		  signed(eee2(15)&eee2(15)&eee2(15)&eee2) +
		  signed(eee3(15)&eee3(15)&eee3(15)&eee3) +
		  signed(eee4(15)&eee4(15)&eee4(15)&eee4) +
		  signed(eee5(15)&eee5(15)&eee5(15)&eee5) +
		  signed(eee6(15)&eee6(15)&eee6(15)&eee6) +
		  signed(eee7(15)&eee7(15)&eee7(15)&eee7);
 end if;
 end if;
end process;

temp2 <= std_ulogic_vector(t2);
t22 <= flag&flag2&flgout2&temp2(18);

process(clk,temp2,t2)
  begin
    if clk'event and clk='1' then
      if ((t22="1100") and ((temp2(17) or temp2(16) or temp2(15) or temp2(14))='1')) then
        llrq(15 downto 0) <= "0011111111111111";
      elsif ((t22="1100") and ((temp2(17) or temp2(16) or temp2(15) or temp2(14))='0')) then
        llrq(15 downto 0)<=temp2(18)&temp2(14 downto 0);
      elsif ((t22="1101") and ((temp2(17) and temp2(16) and temp2(15) and temp2(14))='0')) then
        llrq(15 downto 0)<="1100000000000001";
      elsif ((t22="1101") and ((temp2(17) and temp2(16) and temp2(15) and temp2(14))='1')) then
        llrq(15 downto 0)<=temp2(18)&temp2(14 downto 0);
      else
        llrq(15 downto 0)<=(others=>'0');
      end if;	
	end if;
end process;


end bev;